/**
 * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

/** HP_ALIVE_SYS_HP_CLK_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_CLK_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x0)
/** HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN : R/W; bitpos: [17]; default: 1;
 *  XTALx2 80M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN    (BIT(17))
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_M  (HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V << HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S  17
/** HP_ALIVE_SYS_HP_ROOT_CLK_EN : R/W; bitpos: [18]; default: 1;
 *  HP SoC Root Clock Enable.
 */
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN    (BIT(18))
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_M  (HP_ALIVE_SYS_HP_ROOT_CLK_EN_V << HP_ALIVE_SYS_HP_ROOT_CLK_EN_S)
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_S  18
/** HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN : R/W; bitpos: [19]; default: 1;
 *  XTAL 32K Clock Enable.
 */
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN    (BIT(19))
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_M  (HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S  19
/** HP_ALIVE_SYS_HP_RC_32K_CLK_EN : R/W; bitpos: [20]; default: 1;
 *  RC 32K Clock Enable.
 */
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN    (BIT(20))
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_M  (HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V << HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S  20
/** HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN : R/W; bitpos: [21]; default: 1;
 *  SOSC 150K Clock Enable.
 */
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN    (BIT(21))
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_M  (HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V << HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S  21
/** HP_ALIVE_SYS_HP_PLL_80M_CLK_EN : R/W; bitpos: [22]; default: 1;
 *  PLL 8M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN    (BIT(22))
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_M  (HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V << HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S  22
/** HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [23]; default: 1;
 *  AUDIO PLL Clock Enable.
 */
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN    (BIT(23))
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_M  (HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V << HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S)
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S  23
/** HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [24]; default: 1;
 *  reserved
 */
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN    (BIT(24))
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S  24
/** HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [25]; default: 1;
 *  reserved
 */
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN    (BIT(25))
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S  25
/** HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [26]; default: 1;
 *  reserved
 */
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN    (BIT(26))
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S  26
/** HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN : R/W; bitpos: [27]; default: 1;
 *  FOSC 20M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN    (BIT(27))
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_M  (HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V << HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S  27
/** HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN : R/W; bitpos: [28]; default: 1;
 *  XTAL 40M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN    (BIT(28))
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_M  (HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S  28
/** HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN : R/W; bitpos: [29]; default: 1;
 *  CPLL 300M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN    (BIT(29))
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_M  (HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V << HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S  29
/** HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  SPLL 480M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN    (BIT(30))
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_M  (HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V << HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S  30
/** HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  MPLL 500M Clock Enable.
 */
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_M  (HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V << HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x4)
/** HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  PARLIO TX Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN    (BIT(30))
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S  30
/** HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  PARLIO RX Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8)
/** HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [31]; default: 1;
 *  I2S0 MCLK Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_M  (HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xc)
/** HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [31]; default: 1;
 *  I2S1 MCLK Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_M  (HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x10)
/** HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  UART0 SLP Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x14)
/** HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  UART1 SLP Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x18)
/** HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  UART2 SLP Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S  31

/** HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG register
 *  HP Clock Control Register.
 */
#define HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x1c)
/** HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  UART3 SLP Clock From Pad Enable.
 */
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S  31

/** HP_ALIVE_SYS_MODEM_CLK_AON_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_MODEM_CLK_AON_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x20)
/** HP_ALIVE_SYS_MODEM_CLK_AON_SEL : R/W; bitpos: [31]; default: 1;
 *  Modem clk aon sel. 0: foscl  1:xtal
 */
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL    (BIT(31))
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_M  (HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V << HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S)
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V  0x00000001U
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S  31

/** HP_ALIVE_SYS_USB_CTRL_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_USB_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x24)
/** HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS : R/W; bitpos: [0]; default: 0;
 *  phy chrgvbus
 */
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS    (BIT(0))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V  0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S  0
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS : R/W; bitpos: [1]; default: 0;
 *  phy dischrgvbus
 */
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS    (BIT(1))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V  0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S  1
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN : R/W; bitpos: [2]; default: 0;
 *  phy dmpulldown
 */
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN    (BIT(2))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V  0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S  2
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN : R/W; bitpos: [3]; default: 0;
 *  phy dppulldown
 */
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN    (BIT(3))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V  0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S  3
/** HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP : R/W; bitpos: [4]; default: 0;
 *  phy idpullup
 */
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP    (BIT(4))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V << HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V  0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S  4

/** HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG register
 *  configure rmemory power in lp system register
 */
#define HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x28)
/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures layer0  hp_sram memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S  0
/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down layer0 hp_sram memory.
 */
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN    (BIT(2))
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S  2
/** HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control layer0 hp_sram memory, disable hardware
 *  control.
 */
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL    (BIT(3))
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S  3
/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 0;
 *  Configures layer1  hp_sram memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S  4
/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
 *  Set this bit to power down layer1 hp_sram memory.
 */
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN    (BIT(6))
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S  6
/** HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
 *  Set this bit to force software control layer1 hp_sram memory, disable hardware
 *  control.
 */
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL    (BIT(7))
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S  7
/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE : R/W; bitpos: [9:8]; default: 0;
 *  Configures layer2  hp_sram memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S  8
/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN : R/W; bitpos: [10]; default: 0;
 *  Set this bit to power down layer2 hp_sram memory.
 */
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN    (BIT(10))
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S  10
/** HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL : R/W; bitpos: [11]; default: 0;
 *  Set this bit to force software control layer2 hp_sram memory, disable hardware
 *  control.
 */
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL    (BIT(11))
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S  11
/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE : R/W; bitpos: [13:12]; default: 0;
 *  Configures layer3  hp_sram memory low power mode in low power stage.
 *  0(default): deep sleep
 *  1: light sleep
 *  2: shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S  12
/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN : R/W; bitpos: [14]; default: 0;
 *  Set this bit to power down layer3 hp_sram memory.
 */
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN    (BIT(14))
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S  14
/** HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL : R/W; bitpos: [15]; default: 0;
 *  Set this bit to force software control layer3 hp_sram memory, disable hardware
 *  control.
 */
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL    (BIT(15))
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S  15

/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG register
 *  configure rmemory power in lp system register
 */
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x2c)
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures flash_mmu memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S  0
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down flash_mmu memory.
 */
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN    (BIT(2))
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S  2
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control flash_mmu memory, disable hardware control.
 */
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S  3

/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG register
 *  configure rmemory power in lp system register
 */
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x30)
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures psram_mmu memory low power mode in low power stage.
 *  0: deep sleep
 *  1: light sleep
 *  2(default): shut down
 *  3: disable low power stage
 */
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE    0x00000003U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V  0x00000003U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S  0
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
 *  Set this bit to power down psram_mmu memory.
 */
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN    (BIT(2))
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V  0x00000001U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S  2
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
 *  Set this bit to force software control psram_mmu memory, disable hardware control.
 */
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL    (BIT(3))
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V  0x00000001U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S  3

/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG register
 *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
 */
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x34)
/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
 *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
 */
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG register
 *  sprf mem aux ctrl , control TOP/CNNT power domain
 */
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x38)
/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
 *  sprf mem aux ctrl , control TOP/CNNT/MODEM power domain
 */
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x40)
/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
 *  sdprf mem aux ctrl , control TOP/CNNT/MODEM power domain
 */
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x44)
/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
 *  sprom mem aux ctrl , control CPU power domain
 */
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x48)
/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
 *  need_des
 */
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG register
 *  intr hp2lp configuration register 0
 */
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x7c)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_0 : R/W; bitpos: [31:0]; default: 4294967295;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_0_V << HP_ALIVE_SYS_INTR_HP2LP_EN_0_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG register
 *  intr hp2lp configuration register 1
 */
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x80)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_1 : R/W; bitpos: [31:0]; default: 4294967295;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_1_V << HP_ALIVE_SYS_INTR_HP2LP_EN_1_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG register
 *  intr hp2lp configuration register 2
 */
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x84)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_2 : R/W; bitpos: [31:0]; default: 4294967295;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_2_V << HP_ALIVE_SYS_INTR_HP2LP_EN_2_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG register
 *  intr hp2lp configuration register 3
 */
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x88)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_3 : R/W; bitpos: [31:0]; default: 4294967295;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_3_V << HP_ALIVE_SYS_INTR_HP2LP_EN_3_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG register
 *  intr hp2lp configuration register 4
 */
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8c)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_4 : R/W; bitpos: [7:0]; default: 255;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4    0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_4_V << HP_ALIVE_SYS_INTR_HP2LP_EN_4_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_V  0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG register
 *  intr hp2lp status register 0
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x90)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0 : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG register
 *  intr hp2lp status register 1
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x94)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1 : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG register
 *  intr hp2lp status register 2
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x98)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2 : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG register
 *  intr hp2lp status register 3
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x9c)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3 : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3    0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S  0

/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG register
 *  intr hp2lp status register 4
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa0)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4 : RO; bitpos: [7:0]; default: 0;
 *  reserved
 */
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4    0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V  0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S  0

/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG register
 *  spram mem aux ctrl , control CPU power domain
 */
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa4)
/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
 *  spram mem aux ctrl , control CPU power domain
 */
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S  0

/** HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG register
 *  bus clock gating bypass configuration register
 */
#define HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa8)
/** HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS : R/W; bitpos: [0]; default: 1;
 *  Set 1 to bypass the clock gating for ahb bus
 */
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS    (BIT(0))
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V  0x00000001U
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S  0
/** HP_ALIVE_SYS_APB_CLK_GATING_BYPASS : R/W; bitpos: [1]; default: 1;
 *  Set 1 to bypass the clock gating for apb bus
 */
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS    (BIT(1))
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V  0x00000001U
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S  1
/** HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS : R/W; bitpos: [2]; default: 1;
 *  Set 1 to bypass the clock gating for axi bus
 */
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS    (BIT(2))
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V  0x00000001U
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S  2
/** HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS : R/W; bitpos: [3]; default: 1;
 *  Set 1 to bypass the clock gating for mem bus
 */
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS    (BIT(3))
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V  0x00000001U
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S  3
/** HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS : R/W; bitpos: [4]; default: 1;
 *  Set 1 to bypass the clock gating for ahb mtx
 */
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS    (BIT(4))
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V  0x00000001U
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S  4

/** HP_ALIVE_SYS_RST_EVENT_BYPASS_REG register
 *  bus clock gating bypass configuration register
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xac)
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB : R/W; bitpos: [0]; default: 0;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB    (BIT(0))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S  0
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS : R/W; bitpos: [1]; default: 0;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS    (BIT(1))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S  1
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU : R/W; bitpos: [2]; default: 0;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU    (BIT(2))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S  2
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST : R/W; bitpos: [3]; default: 1;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST    (BIT(3))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S  3
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG : R/W; bitpos: [4]; default: 0;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG    (BIT(4))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S  4
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX : R/W; bitpos: [5]; default: 0;
 *  Set 1 to bypass none-power_on reset source
 */
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX    (BIT(5))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V  0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S  5
/** HP_ALIVE_SYS_RST_BYPASS_LOCK : R/W; bitpos: [6]; default: 0;
 *  Set 1 to lock reset event bypass configuration
 */
#define HP_ALIVE_SYS_RST_BYPASS_LOCK    (BIT(6))
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_M  (HP_ALIVE_SYS_RST_BYPASS_LOCK_V << HP_ALIVE_SYS_RST_BYPASS_LOCK_S)
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_V  0x00000001U
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_S  6

/** HP_ALIVE_SYS_USB_OTGHS_CTRL_REG register
 *  usb_otghs Control configuration register
 */
#define HP_ALIVE_SYS_USB_OTGHS_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xb0)
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN : R/W; bitpos: [0]; default: 0;
 *  Set this bit as 1 to force use reg_usb_otghs_phy_pll_en
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN    (BIT(0))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S  0
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
 *  pll_en for phy inf
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN    (BIT(1))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S  1
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN : R/W; bitpos: [2]; default: 1;
 *  Set this bit as 1 to force use reg_usb_otghs_phy_suspendm
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN    (BIT(2))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S  2
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
 *  phy suspendm
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM    (BIT(3))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S  3
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN : R/W; bitpos: [4]; default: 0;
 *  Set this bit as 1 to force use reg_usb_otghs_phy_reset
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN    (BIT(4))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S  4
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET : R/W; bitpos: [5]; default: 0;
 *  phy reset
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET    (BIT(5))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S  5
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN : R/W; bitpos: [6]; default: 0;
 *  phy txbitstuff_en
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN    (BIT(6))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S  6
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
 *  phy otg_suspendm
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM    (BIT(7))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S  7
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
 *  phy refclk_mode
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE    (BIT(8))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S  8
/** HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE : R/W; bitpos: [10:9]; default: 0;
 *  usb otghs core ss_scaledown_mode
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE    0x00000003U
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V  0x00000003U
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S  9
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST : R/W; bitpos: [11]; default: 0;
 *  phy self_test
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST    (BIT(11))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S  11
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE : RO; bitpos: [12]; default: 0;
 *  phy test_bist
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE    (BIT(12))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S  12
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO : RO; bitpos: [13]; default: 0;
 *  phy dto
 */
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO    (BIT(13))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V  0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S  13

/** HP_ALIVE_SYS_DATE_REG register
 *  need_des
 */
#define HP_ALIVE_SYS_DATE_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x3fc)
/** HP_ALIVE_SYS_DATE : R/W; bitpos: [30:0]; default: 38834448;
 *  need_des
 */
#define HP_ALIVE_SYS_DATE    0x7FFFFFFFU
#define HP_ALIVE_SYS_DATE_M  (HP_ALIVE_SYS_DATE_V << HP_ALIVE_SYS_DATE_S)
#define HP_ALIVE_SYS_DATE_V  0x7FFFFFFFU
#define HP_ALIVE_SYS_DATE_S  0
/** HP_ALIVE_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define HP_ALIVE_SYS_CLK_EN    (BIT(31))
#define HP_ALIVE_SYS_CLK_EN_M  (HP_ALIVE_SYS_CLK_EN_V << HP_ALIVE_SYS_CLK_EN_S)
#define HP_ALIVE_SYS_CLK_EN_V  0x00000001U
#define HP_ALIVE_SYS_CLK_EN_S  31

#ifdef __cplusplus
}
#endif
